1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of supplying a wordline voltage thereof. More particularly, the present invention relates to a semiconductor memory device that includes a wordline voltage generator for supplying a negative wordline voltage and a method of supplying a wordline voltage thereof.
2. Description of Related Art
Semiconductor memory devices are classified into read-only memories (ROMs) and read-and-write memories also called random access memories (RAMs). RAMs are volatile memory devices that lose their contents when the power to them is turned off or interrupted temporarily, while ROMs are non-volatile memory devices in that their contents are not lost when power is removed. There are two basic types of RAM, dynamic RAM (DRAM) and static RAM (SRAM). The different types of ROM include programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory.
In general, each cell of a DRAM includes one capacitor and one MOS transistor. A capacitor is charged when the data is stored in the DRAM cell in the write cycle. As is well known in the art, the capacitor is subject to charge leakage so that the data stored will be lost, unless the charge is refreshed periodically. Therefore, DRAM cells need a so-called “refresh operation” to preserve the data stored. When a semiconductor device operates in a standby or low-power mode, addresses are internally generated to continuously perform a refresh operation for wordlines before a refresh exit command is input. Such a refresh operation is called a self refresh operation.
The need to refresh memory cells can be reduced by decreasing current leakage. One prior art method employs increasing the threshold voltage of the access transistor to suppress current leakage through the transistor. However, with the general trend toward higher integration density and higher speed performance, the voltage level in a semiconductor memory device has an effect on device reliability. For example, the reduced memory cell size results in cell geometries that render the cells subject to damage as higher voltages are applied. In a negative wordline scheme, instead of increasing the threshold voltage of the transistor (and leaving the applied wordline voltage the same), the magnitude of the gate-to-source voltage that is applied to turn off the transistor is increased and the threshold voltage remains unchanged.
FIG. 1 illustrates a DRAM cell employing a negative wordline scheme. Referring to FIG. 1, a negative wordline voltage VWL is applied to the NMOS transistor. The negative wordline voltage is supplied from a wordline voltage generator (not shown).
A conventional wordline voltage generator generates a negative voltage VBB1 that is lower than a ground voltage in response to a standby signal STBY. When a wordline is deactivated, the negative voltage VBB1 is supplied to the wordline to maintain the wordline at a logic low level. Referring to FIG. 1, a wordline voltage VWL is maintained at a voltage level that is half of a negative voltage VBB supplied to a transistor bulk. For example, if a voltage VP applied to a capacitor is 0.8V and a negative voltage VBB applied to a bulk of an NMOS transistor is −0.8V, a negative voltage VBB1 of about −0.4V is applied to a wordline.
However, when a wordline goes to a logic low negative-voltage level, a leakage current Ileak is generated at an NMOS transistor of;a memory cell by gate-induced drain leakage (GIDL). Due to the leakage current Ileak, stored data can be lost and refresh performance deteriorates over time.